The present invention generally relates to semiconductor device manufacturing, and more particularly to fabricating a chip stack using chip-to-wafer bonding.
Assemblies of vertically stacked semiconductor chips having direct vertical electrical interconnections using through silicon vias (TSV) offer improvements in integration density and speed of information access. Wafer-to-wafer bonding techniques can be used to join wafers together in vertically stacked wafer assemblies, which can then be diced into individual stacked semiconductor chip assemblies containing stacks of two or more semiconductor chips each. Chip-to-chip bonding techniques can also be used to join vertically stacked chip assemblies. Chip-to-chip bonding involves separating the semiconductor chips from their respective wafers prior to bonding the chips together in a stack. Chip-to-chip bonding has the benefit that the chips are not constrained by size or aspect ratio, so practically any combination of chips, within reasonable limits, can be bonded together. Chip-to-chip bonding also can be used to bond practically any number of chips together in a stack. Furthermore, chips can be tested prior to bonding, thus enabling defective chips to be sorted out and discarded, thereby providing a higher yield for the overall stack arrangements. Each individual stacked semiconductor chip assembly may have through silicon vias extending in a vertical direction of the assembly for electrically connecting the chips therein.